1. Field of the Invention
This invention relates to a chip scale package (CSP), and more particularly to a chip scale package of semiconductor.
2. Description of Related Art
Following the development of the semiconductor industry, a lot of related new technology is continuously progressing and changing. The manufacturing process of a semiconductor product is generally divided into three stages, firstly the formation of semiconductor base, i.e. the portion of chip-forming technology; secondly, the manufacturing of semiconductor devices such as Metal Oxide Semiconductor (MOS.), the conductive wire inter-connection of stacked metal etc., lastly the packaging process. Today, almost all the efforts on the development of electronic products are heading for the target of light, thin, short. and small in dimension. For examples, these efforts are to raise the degree of intoglation for the semiconductor, and to provide various types of packaging technology such as Chip Scale Package (CSP), Multi-Chip Module (MCM) etc. As the manufacturing technology of semiconductor has progressed to such a tiny width as 0.18 .mu.m of semiconductor elements, the degree of integration has become a great break through. Therefore, how to develop the corresponding tiny packages of semiconductor to achieve the object of minimizing the semiconductor products has become the important topic of study nowadays.
As far as the semiconductor devices of low-number-of-lead are concerned, for examples, high voltage transistor device and identification microchip etc., generally, lead frame is still employed as a chip carrier. Shown in FIG. 1 is a schematic cross-sectional view of the semiconductor package of low-number-of-lead according to the prior art. Take a high voltage transistor device on the circuit board for example, the conventional high voltage transistor device is used for being functioned as a switch. This high voltage transistor device is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having three connecting points, a gate, a source, and a drain.
As shown in FIG. 1, the conventional chip scale package is a Small Outline Transistor (SOT) type with its lead frame possessing four leads 12 and a chip carrier 10. After the chip 16 is bonded to the chip carrier 10, by the use of wire bonding method, bond wire 18 is employed to connect the gate, source, and drain of the chip 16 to the lead 12. Thereafter, a insulated material 20 is employed to encapsulate the chip 16, the chip carrier 10, the bond wire 18, and the inner end of the lead 12. The outer end of the lead 12 is to be formed as a Z-shaped lead (also called as a Gull-Wing type) to facilitate the follow-up SMT (Surface Mount Technique) fabrication.
The conventional chip scale package of the SOT type as described above is quite possible to increase the circuit impedance. Consequently, it will result in signal decay and signal delay since the input/output of the signal is unable to transmit to the chip 10 without passing through the path including the lead and the wire which is relatively lengthy. As far as the mass production type of semiconductor technology of today is concerned, for the MOSELT with 0.4 .mu.m of lead width, the resistance as low as 0.2 mini-ohm-cm has been achieved. However, the resistance of the lead of the conventional chip scale package is as high as 20 mini-ohm-cm that is totally unmatched to the chip, and thereby seriously affecting the performance of the device. In additions, this type of packaging makes the volume of the device increase, the area of application is therefore limited, besides, it contradicts the design principle of light, thin, short, and small in dimension.